An efficient fault diagnosis method for defect-tolerant reconfigurable WSI array architectures is proposed. We use a systolic array as an example array architecture. The basic idea is to utilize the vertical scan paths and horizontal scan paths to partition a two-dimensional systolic array under test into disjoint blocks, and each block can then be tested concurrently, thus the testing time is reduced significantly. A modification version of the reconfigurable array called a full serial scan (FSS) array is also proposed to reduce the hardware overhead of the original design. The significance of our approach is providing an efficient two-dimensional reconfigurable systolic array which is easily diagnosable and the yield enhancement of the array is demonstrated. Furthermore, the design approach can be easily extended to other parallel architectures.