Design for diagnosability and diagnostic strategies of WSI array architectures

Kuo-Chen Wang*, Wang Dauh Tseng

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An efficient fault diagnosis method for defect-tolerant reconfigurable WSI array architectures is proposed. We use a systolic array as an example array architecture. The basic idea is to utilize the vertical scan paths and horizontal scan paths to partition a two-dimensional systolic array under test into disjoint blocks, and each block can then be tested concurrently, thus the testing time is reduced significantly. A modification version of the reconfigurable array called a full serial scan (FSS) array is also proposed to reduce the hardware overhead of the original design. The significance of our approach is providing an efficient two-dimensional reconfigurable systolic array which is easily diagnosable and the yield enhancement of the array is demonstrated. Furthermore, the design approach can be easily extended to other parallel architectures.

Original languageEnglish
Title of host publication1994 IEEE International Conference on Wafer Scale Integration
EditorsMike R. Lea, Stuart Tewksbury
PublisherPubl by IEEE
Pages208-217
Number of pages10
ISBN (Print)0780318501
DOIs
StatePublished - 1 Jan 1994
EventProceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration - San Francisco, CA, USA
Duration: 19 Jan 199421 Jan 1994

Publication series

Name1994 IEEE International Conference on Wafer Scale Integration

Conference

ConferenceProceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration
CitySan Francisco, CA, USA
Period19/01/9421/01/94

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