Design and performance evaluation of a pipelined one-sided crossbar switch

Kuo-Chen Wang*, Ai Yun Liu

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

In this paper, we propose a pipelined one-sided crossbar switch in shared multiprocessor systems. A pipelined interface is the main part of the proposed structure, which controls five phases of our pipelined protocol: arbitration, request, snoop, response, and data. We compare the throughput of four one-sided crossbar switches: pipelined, traditional, modified, and ripple K one-sided crossbar switches. Experimental results show that the maximum throughput (the corresponding waiting time) of an 8 × 8 pipelined one-sided crossbar switch is about 4.8 times higher (0.55 times lower) than that of the other three one-sided crossbar switches. We also evaluate extra buses needed to achieve non-blocking under random and clustered faults for these four switches. In addition, we have described and realized a 4 × 4 pipelined one-sided crossbar switch using Verilog HDL and Xilinx FPGAs, respectively. Verilog simulation results validate the functionality of our pipelined design. The cost-performance (in terms of throughput/area) of our pipelined one-sided crossbar switch is 3.5 times higher than that of the traditional one-sided crossbar switch and 2.8 times higher than that of the other two switches.

Original languageEnglish
Pages (from-to)29-40
Number of pages12
JournalJournal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an
Volume7
Issue number1
StatePublished - 1 Feb 2000

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