Design and optimization of 6T SRAM using vertically stacked nanowire MOSFETs

Ming Fu Tsai, Ming Long Fan, Chia Hao Pao, Yin Nien Chen, Vita Pi Ho Hu, Pin Su, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper discusses the design and optimization of 6T SRAM cell using multiple stacked NanoWire (NW) MOSFETs. The results suggest that RSNM reaches the maximum when Pull-Up (PU) and Pull-Down (PD) transistors are stacked in equivalent number. Up to 40% and 91% improvement in RSNM are achieved at the cost of 7.5% and 5.9% degradation in WSNM using Floating-Power Write-assist compared with the case without stacking at VDD = 0.3V and 1V, respectively. For robust design in subthreshold SRAM, raising Vtrip by stacking PU transistors is more efficient than reducing Read disturb by stacking PD transistors under the premise of using quantized number of stacked NW. Moreover, we show that the stacked NW MOSFETs suppress the impact of Line-Edge Roughness (LER) variation and mitigate the variability in SRAM.

Original languageEnglish
Title of host publication2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
DOIs
StatePublished - 12 Aug 2013
Event2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013 - Hsinchu, Taiwan
Duration: 22 Apr 201324 Apr 2013

Publication series

Name2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013

Conference

Conference2013 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2013
CountryTaiwan
CityHsinchu
Period22/04/1324/04/13

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