Design and iso-area V min analysis of 9T subthreshold SRAM with bit-interleaving scheme in 65-nm CMOS

Ming Hung Chang*, Yi Te Chiu, Wei Hwang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

49 Scopus citations

Abstract

In this brief, a 9T bit cell is proposed to enhance write ability by cutting off the positive feedback loop of a static random-access memory (SRAM) cross-coupled inverter pair. In read mode, an access buffer is designed to isolate the storage node from the read path for better read robustness and leakage reduction. The bit-interleaving scheme is allowed by incorporating the proposed 9T SRAM bit cell with additional write wordlines (WWL/WWLb) for soft-error tolerance. A 1-kb 9T 4-to-1 bit-interleaved SRAM is implemented in 65-nm bulk CMOS technology. The experimental results demonstrate that the test chip minimum energy point occurs at 0.3-V supply voltage. It can achieve an operation frequency of 909 kHz with 3.51-μW active power consumption.

Original languageEnglish
Article number6220865
Pages (from-to)429-433
Number of pages5
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue number7
DOIs
StatePublished - 27 Jun 2012

Keywords

  • Bit-interleaving scheme
  • iso-area analysis
  • subthreshold static random-access memory (SRAM)

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