Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability

Wei Hwang*, G. D. Gristede, P. N. Sanda, S. Y. Wang, D. F. Heidel

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

1 Scopus citations

Abstract

This paper presents a fast, low power, binary carry look-ahead 64-bit dynamic parallel adder architecture for a high frequency microprocessor. The adder core is composed of several basic building blocks and feedback reset chain blocks implemented in self-resetting CMOS (SRCMOS) circuits. All circuits are design with enhanced testability. A new tool, SPA (SRCMOS Pulse Analyzer) is developed for dynamic and static checks. The nominal propagation delay and power dissipation of the adder are measured to be 1.5 ns (at 22 C with Vdd = 2.5 V) and 300 mW. The adder core size is 1.6 mm×0.275 mm. The process that the design is based upon in a 0.5μm IBM CMOS5X technology with 0.25μm effective channel length and 5 layers of metal. The circuit techniques are ready to be migrated to sub-nanosecond microprocessor design.

Original languageEnglish
Pages (from-to)519-522
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 1 Jan 1998
EventProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 11 May 199814 May 1998

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