This paper presents an FPGA-based multiple-loop control scheme for the regulation of the PWM inverters used in UPS. The proposed control scheme incorporates an inner current loop with an outer voltage loop to regulate the output voltage of the PWM inverter, which is expected to be sinusoidal. The corresponding control gains are designed through deadbeat theory so that the inverter can achieve fast dynamic response. An output voltage decoupling mechanism and a load disturbance compensation scheme have been proposed to improve the stiffness of the controlled PWM inverter. The developed digital controller has been realized by a RAM-based FPGA XC4010 to verify its effectiveness. The simulation and experimental results show that the output voltage of the controlled PWM inverter has good transient response and little distortion under rough load conditions.
|Number of pages||6|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 2nd International Conference on Power Electronics and Drive Systems, PEDS. Part 2 (of 2) - Singapore, Singapore|
Duration: 26 May 1997 → 29 May 1997
|Conference||Proceedings of the 1997 2nd International Conference on Power Electronics and Drive Systems, PEDS. Part 2 (of 2)|
|Period||26/05/97 → 29/05/97|