Providing security has become more and more urgent and necessary in embedded systems. To support the functionality security in embedded systems, the issues of the cost of executing the cryptographic algorithms and flexibility concerns must be solved. In the paper, we focus on the three most commonly used cryptographic algorithms, AES, DES and RSA to design a reconfigurable hardware for accelerating the executing the three algorithms. The reconfigurable hardware can be switched its behaviors by the control of configuration contexts to execute the functions of cryptographic algorithms. We first analyze the operation of the three cryptographic algorithms and classified them into three categories. The three modules, permutation and combination unit, computation unit and memory unit, are then designed for processing the three categories of functions. The computation is the main processing module in this architecture and is consisted of many processing elements. In order to design a better processing element for the cost effectively, we design four candidates for the design of the processing elements and evaluate them by using the benchmark. A cost function is also defined to analyze space-time product of the reconfigurable hardware compared with the ASIC design. The experimental result indicates the reconfigurable hardware only use the cost of 78% compared with the ASIC design with the same benchmark. Furthermore, if we take off the internal SRAM in both design and use the system storage area for computation, the reconfigurable design has the cost of only 70% compared with the ASIC design.