Design and implementation of a reconfigurable architecture for (528, 518) Reed-Solomon codec IP

Fuh Ke Chang*, Wei Chun Hsu, Chien Ching Lin, Hsie-Chia Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper, an area-efficient Reed-Solomon (RS) codec IP with composite-field inverter is presented. For some specific applications such as flash memory controller using RS (528,518) code over GF(210) to correct 4 errors, the RS decoder will stop receiving any new codeword until the on-going erroneous codeword to be corrected. It is that the circuit complexity can be reduced by sharing the registers and finite-field operation units. Moreover, the proposed hardware sharing architecture also includes the RS encoder. After implementing by 0.18μm 1P6M standard cell slow library, the RS (528, 518) codec IP totally requires 2 finite-field multiplier, 1 composite-field inverter and 17(=4t+l) registers, where t is the number of correctable errors. In contrast with other architectures, at least 42% circuit complexity can be reduced in our proposal.

Original languageEnglish
Title of host publication3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005
Pages87-90
Number of pages4
DOIs
StatePublished - 1 Dec 2005
Event3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005 - Quebec City, QC, Canada
Duration: 19 Jun 200522 Jun 2005

Publication series

Name3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005
Volume2005

Conference

Conference3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005
CountryCanada
CityQuebec City, QC
Period19/06/0522/06/05

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