Design and implementation of a high-performance and complexity-effective VLIW DSP for multimedia applications

Tay Jyi Lin*, Shin Kai Chen, Yu Ting Kuo, Chih-Wei Liu, Pi Chen Hsiao

*Corresponding author for this work

Research output: Contribution to journalArticle

14 Scopus citations

Abstract

This paper presents the design and implementation of a novel VLIW digital signal processor (DSP) for multimedia applications. The DSP core embodies a distributed & ping-pong register file, which saves 76.8% silicon area and improves 46.9% access time of centralized ones found in most VLIW processors by restricting its access patterns. However, it still has comparable performance (estimated in cycles) with state-of-the-art DSP for multimedia applications. A hierarchical instruction encoding scheme is also adopted to reduce the program sizes to 24.1 ∼ 26.0%. The DSP has been fabricated in the UMC 0.13 μm 1P8M Copper Logic Process, and it can operate at 333 MHz while consuming 189 mW power. The core size is 3.2∈×∈3.15 mm 2 including 160 KB on-chip SRAM.

Original languageEnglish
Pages (from-to)209-223
Number of pages15
JournalJournal of Signal Processing Systems
Volume51
Issue number3
DOIs
StatePublished - 1 Jun 2008

Keywords

  • Digital signal processor
  • Instruction encoding
  • Micro-architecture
  • Register organization
  • VLIW

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