Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGe heterostructure channel

Yee Chia Yeo*, Vivek Subramanian, Jakub Kedzierski, Peiqi Xuan, Tsu Jae King, Jeffrey Bokor, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

32 Scopus citations

Abstract

Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short-channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorporation of Si 0.7Ge 0.3 in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure-channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel.

Original languageEnglish
Pages (from-to)279-286
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume49
Issue number2
DOIs
StatePublished - 1 Feb 2002

Keywords

  • Heterojunctions
  • MOSFETs
  • SiGe
  • Strain
  • Thin-body

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