Design and anaylsis of A 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology

Wei-Zen Chen*, Chao Hsin Lu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

47 Scopus citations

Abstract

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-μm digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8μArms. The input sensitivity of the receiver front-end is 16 μA 2.5-Gbps operation with bit-error rate less than 10-12 and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is μm × 1500 μm.

Original languageEnglish
Pages (from-to)977-983
Number of pages7
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume53
Issue number5
DOIs
StatePublished - 1 May 2006

Keywords

  • Active inductor
  • Amplifier (TIA)
  • Limiting amplifier (LA)
  • Transimpedance

Fingerprint Dive into the research topics of 'Design and anaylsis of A 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology'. Together they form a unique fingerprint.

Cite this