An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1 V. The device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only approximately 1.0 pF (including the bond pad capacitance) for high-frequency applications.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 28 May 2000|
|Event||Proceedings of the IEEE 2000 International Symposium on Circuits and Systems - Geneva, Switz|
Duration: 28 May 2000 → 31 May 2000