Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications

Ming-Dou Ker*, Tung Yang Chen, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ∼1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.

Original languageEnglish
Pages (from-to)257-278
Number of pages22
JournalAnalog Integrated Circuits and Signal Processing
Volume32
Issue number3
DOIs
StatePublished - 1 Sep 2002

Keywords

  • Analog pin
  • Electrostatic discharge (ESD)
  • ESD protection circuit
  • Input capacitance

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