Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process

Ming-Dou Ker*, Tai Xiang Lai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.25-μm salicided CMOS process to find optimum layout rules for CDE protection. From the measured results, the CDE robustness of CMOS devices is much worse than their HBM ESD robustness.

Original languageEnglish
Title of host publication2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual
Pages633-634
Number of pages2
DOIs
StatePublished - 1 Dec 2006
Event44th Annual IEEE International Reliability Physics Symposium, IRPS 2006 - San Jose, CA, United States
Duration: 26 Mar 200630 Mar 2006

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference44th Annual IEEE International Reliability Physics Symposium, IRPS 2006
CountryUnited States
CitySan Jose, CA
Period26/03/0630/03/06

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