Denser and more stable FinFET SRAM using multiple fin heights

Angada B. Sachid*, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

Stability and integration density are two important SRAM performance metrics. A well designed SRAM cell has high stability and high integration density. Stability and integration density are competing parameters. Increasing the stability usually requires increasing the width of the access (AC) transistor, which decreases the integration density. SRAM occupies a high percentage of chip area in modern-day chips. Any method to decrease the cell area increases the integration density of the chip, and potentially decreases the cost. Traditional scaling relied on decreasing the device dimensions by 0.7 to decrease the area by 0.5. In the recent times, as the gate length (L G) scaling slowed down, techniques like thin-cell layouts and Self-Aligned Contacts (SAC) are used to maintain the area scaling trend [1]. We propose an SRAM cell with Selectively-Recessed Shallow-Trench Isolation (SR-STI) FinFET to improve the stability and decrease cell area.

Original languageEnglish
Title of host publication2011 International Semiconductor Device Research Symposium, ISDRS 2011
DOIs
StatePublished - 1 Dec 2011
Event2011 International Semiconductor Device Research Symposium, ISDRS 2011 - College Park, MD, United States
Duration: 7 Dec 20119 Dec 2011

Publication series

Name2011 International Semiconductor Device Research Symposium, ISDRS 2011

Conference

Conference2011 International Semiconductor Device Research Symposium, ISDRS 2011
CountryUnited States
CityCollege Park, MD
Period7/12/119/12/11

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