Software-based cache coherence scheme is very desirable in scalable multiprocessor as well as massively parallel processor designs. In this paper we propose a software-based cache coherence scheme named delayed precise invalidation. The delayed precise invalidation is based on compiler time markings of references and a hardware-based local explicit invalidation of stale data in parallel and selectively. With a small amount of additional hardware and a small set of cache management instructions, the delayed precise invalidation provides more cacheability and allows invalidation of partial elements in an array, overcoming some of the inefficiencies and deficiencies of previous schemes. A correctness proof and a qualitative performance evaluation of the proposed scheme are also presented. Finally, the simulated cache hit ratios of the delayed precise invalidation and the parallel explicit invalidation scheme  are given. Simulation results show that the delayed precise invalidation outperforms the parallel explicit invalidation scheme by 10%.
|Title of host publication||Proceedings of 1994 International Conference on Parallel and Distributed Systems|
|Number of pages||6|
|State||Published - 19 Dec 1994|
|Event||Proceedings of the 1994 International Conference on Parallel and Distributed Systems - Hsinchu, China|
Duration: 19 Dec 1994 → 21 Dec 1994
|Conference||Proceedings of the 1994 International Conference on Parallel and Distributed Systems|
|Period||19/12/94 → 21/12/94|