Delay variation tolerance for domino circuits

Kai-Chiang Wu*, Cheng Tao Hsieh, Shih Chieh Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Factors of delay variation, such as process variation and noise effects, may cause a manufactured chip to violate the pre-specified timing constraint. In this paper, we propose a novel re-synthesis technique to tolerate delay variation for domino circuits. Note that the slacks of nodes along critical paths are zero; any delay addition to those zero-slack nodes will worsen the final performance of a circuit. Our basic idea is to increase the slacks of nodes in the critical region by appending a redundant auxiliary sub-circuit to the original circuit. The auxiliary sub-circuit can cause critical paths to become false paths or imperceptible paths [7] so as to improve the capability of delay variation tolerance. Experimental results are very encouraging.

Original languageEnglish
Title of host publicationProceedings of the ASP-DAC 2006
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2006
Pages354-359
Number of pages6
DOIs
StatePublished - 19 Sep 2006
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
Duration: 24 Jan 200627 Jan 2006

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2006

Conference

ConferenceASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
CountryJapan
CityYokohama
Period24/01/0627/01/06

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  • Cite this

    Wu, K-C., Hsieh, C. T., & Chang, S. C. (2006). Delay variation tolerance for domino circuits. In Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 (pp. 354-359). [1594708] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006). https://doi.org/10.1109/ASPDAC.2006.1594708