Delay Models and Speed Improvement Techniques for RC Tree Interconnections Among Small-Geometry CMOS Inverters

Chung-Yu Wu, Ming Chuen Shiau

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

Physical delay models entirely based upon device equations for small-geometry CMOS inverters with RC tree interconnection networks are presented. Through extensive comparisons with SPICE simulation results, it is shown that the maximum relative error in delay-time calculations using the developed model is within 15% for 1.5-μm CMOS inverters with RC tree interconnection networks. Moreover, the model has a wide applicable range of circuit and device parameters. Based upon the developed models and the mathematic optimization method, an experimental sizing program is constructed for speed improvement of interconnection lines and trees. In this program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed improvement techniques and determine the suitable sizes and/or number of drivers/ repeaters for a minimum delay. The four speed improvement techniques use minimum-size repeaters, optimal-size repeaters, cascaded input drivers, and optimal-size repeaters with cascaded input drivers to reduce the interconnection delay. It is found from the sizing results of the experimental program that the required tapering factor in cascaded drivers is not e (the base of the natural logarithm) but a value in the range of 4–8. Moreover, adding a small number of drivers/repeaters with large sizes is more efficient in reducing the interconnection delay. It is also shown that the technique of optimal-size repeaters with cascaded input drivers can lead to the lowest delay.

Original languageEnglish
Pages (from-to)1247-1256
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume25
Issue number5
DOIs
StatePublished - 1 Jan 1990

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