Physical timing models of bipolar CML logic circuits have been developed and successfully applied to the delay analysis and calculation. Moreover, useful design guidelines, requirements, and limitations of CML gates have also been developed. It is expected that the models could be applied in CAD of bipolar VLSI. They could also be extended to model the delay of other bipolar CML-like logic circuits.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Dec 1991|
|Event||1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore|
Duration: 11 Jun 1991 → 14 Jun 1991