Delay modeling and design considerations of bipolar multi-input CML gates

Tain Shun Wu*, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

Physical timing models of bipolar CML logic circuits have been developed and successfully applied to the delay analysis and calculation. Moreover, useful design guidelines, requirements, and limitations of CML gates have also been developed. It is expected that the models could be applied in CAD of bipolar VLSI. They could also be extended to model the delay of other bipolar CML-like logic circuits.

Original languageEnglish
Pages (from-to)2685-2688
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
DOIs
StatePublished - 1 Dec 1991
Event1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore
Duration: 11 Jun 199114 Jun 1991

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