Degradation of the capacitance-voltage behaviors of the low-temperature polysilicon TFTs under DC stress

Ya-Hsiang Tai*, Shih Che Huang, Chien Wen Lin, Hao Lin Chiu

*Corresponding author for this work

Research output: Contribution to journalArticle

29 Scopus citations

Abstract

In this paper, the degradation of n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under dc stress is investigated with measurement of the capacitance between the source and the gate (CGS), as well as the capacitance between the drain and the gate (CGD). It is discovered that the degradation in CGD curves of the device after hot carrier stress shows apparent frequency dependence, while that in the CGS curves remains almost the same. A circuit model based on the channel resistance extracted from the current-voltage behavior is proposed to describe the frequency dependence of the capacitance behavior. From this model, it is revealed that the anomalous frequency-dependent capacitance-voltage characteristics may simply reflect the transient behaviors of the channel resistances. Besides, it was found that the CGS curves after self-heating effect exhibit a significant shift in the positive direction and an additional increase for the smaller gate voltage, while the CGD curves show only positive shifts. By employing simulation, it was proved that the self-heating effect creates interface states near the source region and increases the deep states in the poly-Si film near drain. The proposed circuit model further explains the behavior of the CGS and CGD curves for the stressed device at different measuring frequencies.

Original languageEnglish
JournalJournal of the Electrochemical Society
Volume154
Issue number7
DOIs
StatePublished - 11 Jun 2007

Fingerprint Dive into the research topics of 'Degradation of the capacitance-voltage behaviors of the low-temperature polysilicon TFTs under DC stress'. Together they form a unique fingerprint.

  • Cite this