This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.
|Number of pages||7|
|Journal||Proceedings of SPIE-The International Society for Optical Engineering|
|State||Published - 1 Jan 2002|
- Defect detection
- Logic process
- Test structure design