Defect detection for short-loop process and SRAM-cell optimization by using Addressable Failure Site Test Structures (AFS-TS)

Kelvin Yih Yuh Doong, Sunnys Hsieh, S. C. Lin, J. R. Wang, Binson Shen, L. J. Hung, Jyh-Chyurn Guo, I. C. Chen, K. L. Young, Charles Ching-Hsiang Hsu

Research output: Contribution to journalArticle

Abstract

This work describes the utilization of a novel test structure called addressable failure site test structure for short-loop defect detection and proposed a prototype test structure for SRAM process defect detection in advanced semiconductor manufacturing. The novel test structures are used to identify the locations of killer defects which are then used to wafer map defect sites. This simple and efficient killer defect identification of process steps is employed as yield enhancement strategy.

Original languageEnglish
Pages (from-to)81-87
Number of pages7
JournalProceedings of SPIE-The International Society for Optical Engineering
Volume4692
DOIs
StatePublished - 1 Jan 2002

Keywords

  • Defect detection
  • Logic process
  • SRAM
  • Test structure design
  • WAT

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