Decentralized BIST for 1149.1 and 1149.5 based interconnects

Chau-Chin Su, Shyh-Jye Jou, Yuan Tzu Ting

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

This paper presents a decentralized BIST methodology for system level interconnects. For 3-state nets, we interleave pseudorandom counting sequences (PCS) and walking sequences to avoid the conflict among multiple drivers of a net. For multiple scan chains, each chain is applied with a particular window of the PCS to ensure the distinctness of every test vector and 100% stuck-at and short faults coverage for nets across scan chains and/or board boundaries. The synchronization of chains of different lengths is handled gracefully by inserting a preamble to make all the chains the same length.

Original languageEnglish
Title of host publicationProceedings of the 1996 European Conference on Design and Test, EDTC 1996
PublisherAssociation for Computing Machinery, Inc
Pages120-125
Number of pages6
ISBN (Electronic)0818674237, 9780818674235
DOIs
StatePublished - 11 Mar 1996
Event1996 European Conference on Design and Test, EDTC 1996 - Paris, France
Duration: 11 Mar 199614 Mar 1996

Publication series

NameProceedings of the 1996 European Conference on Design and Test, EDTC 1996

Conference

Conference1996 European Conference on Design and Test, EDTC 1996
CountryFrance
CityParis
Period11/03/9614/03/96

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