DeAr: A framework for power-efficient and flexible embedded digital signal processor design

Chi Ming Lee, Yong Jyun Huang, Chih-Wei Liu, Yarsun Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The evolution of wireless communication protocols drives the quest of power-efficient and flexible computing for embedded DSPs, but popular architectures, very-long-instruction-word (VLIW) and application-specific instruction set processor (ASIP), serve as opposite extreme cases in regard to power-efficiency and flexibility. To this end, we present DeAr: Dual-thread Architecture DSP, which manipulates a multi-banked register file that enables simultaneous multi-threading (SMT), and a transport-triggered bus that exploits the data forwarding mechanism in its compact datapath. We also propose a novel scheduling algorithm which leverages the compact hardware to achieve both high throughput and flexible computation. In the experiment of common DSP kernels, DeAr saves 20.3%-13.1% and 31.8%-2.2% of power dissipation, 36.1%-31.5% and 28.2%-5.7% of area, compared with VLIW and ASIP respectively.

Original languageEnglish
Title of host publication2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages658-661
Number of pages4
ISBN (Electronic)9781509015702
DOIs
StatePublished - 3 Jan 2017
Event2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 - Jeju, Korea, Republic of
Duration: 25 Oct 201628 Oct 2016

Publication series

Name2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016

Conference

Conference2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
CountryKorea, Republic of
CityJeju
Period25/10/1628/10/16

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