Dead via minimization by simultaneous routing and redundant via insertion

Chih Ta Lin*, Yen Hung Lin, Guan Chan Su, Yih-Lang Li

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

While via failure significantly contributes to yield loss during manufacturing, post-routing redundant via insertion method is the conventional means of reducing the via failure rate, but only alive vias can be protected. As existing dead vias still lower manufacturing yield, identifying a routing result with fewer dead vias can increase the redundant via insertion rate, subsequently enhancing the yield of chips. This work presents, for the first time, a redundant-via-aware routing system to retain redundant via resources in track assignment, in which redundant vias are inserted in detailed routing. The proposed via prediction scheme performs trial route using L-shaped patterns to estimate via positions. Meanwhile, the proposed redundant-via-aware detailed router gradually relaxes the limitation on the number of generated dead vias during path searching to minimize the number of dead vias. Experimental results indicate that the proposed redundant-via-aware routing system is, to our knowledge, the first routing system that can achieve 100% redundant via insertion rate with all MCNC benchmark circuits.

Original languageEnglish
Title of host publication2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages657-662
Number of pages6
DOIs
StatePublished - 28 Apr 2010
Event2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan
Duration: 18 Jan 201021 Jan 2010

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
CountryTaiwan
CityTaipei
Period18/01/1021/01/10

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