A lightweight, low-power, real-time data compressor design for the Earth Observing System (EOS) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-μm CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.
|Number of pages||6|
|State||Published - 1 Dec 1989|
|Event||IGARSS'89 - Twelfth Canadian Symposium on Remote Sensing Part 3 (of 5) - Vancouver, BC, Can|
Duration: 10 Jul 1989 → 14 Jul 1989
|Conference||IGARSS'89 - Twelfth Canadian Symposium on Remote Sensing Part 3 (of 5)|
|City||Vancouver, BC, Can|
|Period||10/07/89 → 14/07/89|