DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction

Dave Y.W. Lin*, Charles H.P. Wen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

For the safety-critical applications such as biomedical and automobile electronics, the system failure induced by soft errors becomes a major issue of reliability. However, most of the commercial cell libraries do not include radiation-hardened components to build a safety-critical design. Therefore, a delay-adjustable D-flip-flop (DAD-FF) is proposed together with a design flow to construct a radiation-hardened system by automation. To enable such radiation-hardened design into the current design flow, DAD-FF is characterized as a general cell and compiled as a patch in the NanGate FreePDK45 bulk 45-nm open cell library, as an example. The experimental results show that DAD-FF is capable of reducing 1.3\times 10^{10}\text{X} soft errors with respect to the standard flip-flop (STD-FF) and resisting over 99.999997% strikes of heavy ions. Meanwhile, four radiation-hardened benchmark circuits are synthesized with DAD-FF cell, and further used to prove the effectiveness against soft errors compared to a prior work, built-in soft-error resilience (BISER), with 18% area and 40% timing improvement. To sum up, DAD-FF is elaborated from the modeling at the device-level to the validation at the system-level and exhibits its strong robustness to soft errors.

Original languageEnglish
Article number8959402
Pages (from-to)1030-1042
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume28
Issue number4
DOIs
StatePublished - Apr 2020

Keywords

  • Characterization
  • design flow
  • flip-flops
  • heavy ion
  • radiation hardening
  • semiconductor device modeling
  • singleevent transient (SET)
  • soft error
  • technology computer-aided design (TCAD) simulation

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