Abstract
A new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. This abrupt degradation is believed due to the creation of a new soft breakdown path in a switching dielectric by cycling stress. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. This cycling-induced degradation mode imposes a serious constraint on the number of SET-disturb pulses and thus an endurance cycle number in a resistive switching memory.
Original language | English |
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Article number | 6994811 |
Pages (from-to) | 135-137 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 36 |
Issue number | 2 |
DOIs | |
State | Published - 1 Feb 2015 |
Keywords
- degradation
- over-SET
- RRAM
- SET-disturb