Cycling-induced SET-disturb failure time degradation in a resistive switching memory

Yueh Ting Chung, Po Cheng Su, Yu Hsuan Cheng, Ta-Hui Wang, Min Cheng Chen, Chih Yuan Lu

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

A new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. This abrupt degradation is believed due to the creation of a new soft breakdown path in a switching dielectric by cycling stress. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. This cycling-induced degradation mode imposes a serious constraint on the number of SET-disturb pulses and thus an endurance cycle number in a resistive switching memory.

Original languageEnglish
Article number6994811
Pages (from-to)135-137
Number of pages3
JournalIEEE Electron Device Letters
Volume36
Issue number2
DOIs
StatePublished - 1 Feb 2015

Keywords

  • degradation
  • over-SET
  • RRAM
  • SET-disturb

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