Cycling induced degradation of a 65nm FPGA Flash memory switch

Ben A. Schmid, James Yingbo Jia, Jonathan Wolfman, Yu Wang, Fethi Dhaoui, Huan Chung Tseng, Sung Rae Kim, Kin Sing Lee, Patty Liu, Kyung Joon Han, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

We present a study of cycling induced degradation of a two transistor Flash memory cell with a shared floating gate. The cell directly serves as a configurable interconnection switch in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. By optimizing the poly re-oxidation, LDD implant and spacer module, the cell endurance is significantly improved at both the single cell and 1 Mbit test-array levels.

Original languageEnglish
Title of host publication2010 IEEE International Integrated Reliability Workshop Final Report, IIRW 2010
Pages92-94
Number of pages3
DOIs
StatePublished - 1 Dec 2010
Event2010 IEEE International Integrated Reliability Workshop, IIRW 2010 - South Lake Tahoe, CA, United States
Duration: 17 Oct 201021 Oct 2010

Publication series

NameIEEE International Integrated Reliability Workshop Final Report

Conference

Conference2010 IEEE International Integrated Reliability Workshop, IIRW 2010
CountryUnited States
CitySouth Lake Tahoe, CA
Period17/10/1021/10/10

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