Cycle time estimation for semiconductor final testing processes with Weibull-distributed waiting time

Accurate cycle time is an essential planning basis required for many production applications, especially on due date commitments, performance metrics analysing, capacity planning, and scheduling. The re-entrant final testing process is the final stage of the complicated semiconductor manufacturing process. To enhance the ability of quick responses and to achieve better on-time delivery in final testing factories, it is essential to develop an accurate cycle time estimation method. In this paper, we provide a statistical approach to calculate the cycle time for multi-layer semiconductor final testing involving the sum of multiple Weibull-distributed waiting times. In addition, percentiles of the cycle time are obtained which are useful to industrial practitioners for due date commitments satisfying the targeted on-time delivery rate. To demonstrate the applicability of the proposed cycle time estimation model, a real example in a semiconductor final testing factory which is located on the Science-based Industrial Park in Hsinchu, Taiwan, is presented.