Crosstalk-aware power optimization with multi-bit flip-flops

Chih Cheng Hsu*, Yao Tsung Chang, Po-Hung Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique. Many previous works tried to utilize as more MBFFs with larger bit numbers as possible to gain more clock power saving. However, an MBFF with a larger bit number may lead to serious crosstalk due to the close interconnecting wires belonging to different signal nets which are connected to the same MBFF. To address the problem, this paper analyzes, evaluates, and compares the relationship between power consumption and crosstalk when applying MBFFs with different bit numbers. To solve the addressed problem, a novel crosstalk-aware power optimization approach is further proposed to optimize power consumption while satisfying the crosstalk constraint. Experimental results show that the proposed approach is very effective in crosstalk avoidance when applying MBFFs for power optimization. To our best knowledge, this is also the first work in the literature that considers the crosstalk effect for the MBFF application.

Original languageEnglish
Title of host publicationASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages431-436
Number of pages6
DOIs
StatePublished - 26 Apr 2012
Event17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia
Duration: 30 Jan 20122 Feb 2012

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
CountryAustralia
CitySydney, NSW
Period30/01/122/02/12

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