Crossroad system-on-chip communication architecture for low power embedded systems

Kuei Chung Chang*, Jih Shen Shen, Tien-Fu Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

As the number of modules on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The disadvantages of shared-bus architectures are larger load per data-bus line, longer delay for data transfer, large energy consumption, and lower bandwidth. This paper proposes a novel interconnect architecture, which dynamically construct a dedicated communication path between any two modules by crossroad switches. In the case of data being transferred between two modules, the energy consumption is significantly reduced because there are no switching activities in other bus segments. Switches can also construct two parallel communication paths at the same time to enhance the communication performance. Experimental results showed that the crossroad bus architecture could save the energy consumption approximated to 31%.

Original languageEnglish
Title of host publicationProceedings of the 2005 International Conference on Embedded Systems and Applications, ESA'05
Pages151-157
Number of pages7
StatePublished - 1 Dec 2005
Event2005 International Conference on Embedded Systems and Applications, ESA'05 - Las Vegas, NV, United States
Duration: 27 Jun 200530 Jun 2005

Publication series

NameProceedings of the 2005 International Conference on Embedded Systems and Applications, ESA'05

Conference

Conference2005 International Conference on Embedded Systems and Applications, ESA'05
CountryUnited States
CityLas Vegas, NV
Period27/06/0530/06/05

Keywords

  • Low power
  • NoC
  • Segment bus
  • Switch

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