Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors

Po Hao Wang*, Shang Jen Tsai, Rizal Tanjung, Tay Jyi Lin, Jinn Shyan Wang, Tien-Fu Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

Voltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration.

Original languageEnglish
Pages (from-to)24-36
Number of pages13
JournalIntegration, the VLSI Journal
Volume54
DOIs
StatePublished - 1 Jun 2016

Keywords

  • Cache memory
  • Low voltage
  • Timing discrepancy
  • Timing-failure tolerance

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