In deep submicron era, wire delay is no longer negligible and is dominating the system performance. Several tate-of-the-art architectural synthesis flows have been proposed or the distributed register architectures to cope with the ncreasing wire delay by allowing on-chip multicycle communication. In this paper, we present a new performancedriven criticality-aware synthesis flow CriAS targeting regular istributed register architectures. CriAS features a hierarchical inding strategy and a coarse-grained placer for minimizing the umber of critical global data transfers. The key ideas are to ake time criticality as the major concern at earlier binding tages before the detailed physical placement information is available, and to preserve the locality of closely related critical omponents in the later placement phase. The experimental esults show that 19% overall performance improvement can be chieved on average as compared to the previous work.