With feature sizes on chips shrinking at advanced process nodes, the difficulty in manufacturability and reliability of chips is extremely increasing. It has necessitated better planarization of chip surface topography to improve both functional and parametric yields. The common solution to minimize topography variation is to perform metal fills in empty spaces in the layout. However, these dummy metals will increase the capacitances between wires and then invoke delay and coupling/crosstalk noise problems. Furthermore, the impact of ECP (electroplating) should be included in the copper CMP model in order to have accurate metal fill results. In this paper, we adopt and implement an approach to considering especially the key layout parameters that affect the post-ECP topography. We further apply a greedy-based method to place the floating dummy metals in the positions with minimal additional coupling capacitances. The experimental results are encouraging. Our method not only considers the thickness range of post-ECP, it can also add much less additional coupling capacitances over a density-driven metal fill method.