Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches

Ying Liang Chen, Terng Yin Hsu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we disclosure a cost-efficiency FFT via hardware-reduction and dynamic current scaling (DCS) schemes in a low-power OFDM modem. These reductions are realized by the pipelined data path modifying and the hardware sharing at two stages. For low power, the operating current is scalable to reduce power consumption, namely DCS. All our works are synthesized and simulated by the TSMC 65nm CMOS technology. It can perform high efficient computing power at FFTs/Energy.

Original languageEnglish
Title of host publicationProceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages184-187
Number of pages4
ISBN (Electronic)9781479948338
DOIs
StatePublished - 2 Feb 2015
Event14th International Symposium on Integrated Circuits, ISIC 2014 - Singapore, Singapore
Duration: 10 Dec 201412 Dec 2014

Publication series

NameProceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014

Conference

Conference14th International Symposium on Integrated Circuits, ISIC 2014
CountrySingapore
CitySingapore
Period10/12/1412/12/14

Keywords

  • Dynamic Current Scaling (DCS)
  • Fast Fourier Transform (FFT)
  • Pipelined-based Architecture

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