Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches

Ying Liang Chen; Terng Yin Hsu

doi:10.1109/ISICIR.2014.7029577

Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches

Ying Liang Chen, Terng Yin Hsu

Institute of Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, we disclosure a cost-efficiency FFT via hardware-reduction and dynamic current scaling (DCS) schemes in a low-power OFDM modem. These reductions are realized by the pipelined data path modifying and the hardware sharing at two stages. For low power, the operating current is scalable to reduce power consumption, namely DCS. All our works are synthesized and simulated by the TSMC 65nm CMOS technology. It can perform high efficient computing power at FFTs/Energy.

Original language	English
Title of host publication	Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	184-187
Number of pages	4
ISBN (Electronic)	9781479948338
DOIs	https://doi.org/10.1109/ISICIR.2014.7029577
State	Published - 2 Feb 2015
Event	14th International Symposium on Integrated Circuits, ISIC 2014 - Singapore, Singapore Duration: 10 Dec 2014 → 12 Dec 2014

Publication series

Name	Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014

Conference

Conference	14th International Symposium on Integrated Circuits, ISIC 2014
Country	Singapore
City	Singapore
Period	10/12/14 → 12/12/14

Keywords

Dynamic Current Scaling (DCS)
Fast Fourier Transform (FFT)
Pipelined-based Architecture

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Chen, Y. L., & Hsu, T. Y. (2015). Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches. In Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014 (pp. 184-187). [7029577] (Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISICIR.2014.7029577

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abstract = "In this paper, we disclosure a cost-efficiency FFT via hardware-reduction and dynamic current scaling (DCS) schemes in a low-power OFDM modem. These reductions are realized by the pipelined data path modifying and the hardware sharing at two stages. For low power, the operating current is scalable to reduce power consumption, namely DCS. All our works are synthesized and simulated by the TSMC 65nm CMOS technology. It can perform high efficient computing power at FFTs/Energy.",

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Chen, YL & Hsu, TY 2015, Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches. in Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014., 7029577, Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014, Institute of Electrical and Electronics Engineers Inc., pp. 184-187, 14th International Symposium on Integrated Circuits, ISIC 2014, Singapore, Singapore, 10/12/14. https://doi.org/10.1109/ISICIR.2014.7029577

Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches. / Chen, Ying Liang; Hsu, Terng Yin.

Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014. Institute of Electrical and Electronics Engineers Inc., 2015. p. 184-187 7029577 (Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, we disclosure a cost-efficiency FFT via hardware-reduction and dynamic current scaling (DCS) schemes in a low-power OFDM modem. These reductions are realized by the pipelined data path modifying and the hardware sharing at two stages. For low power, the operating current is scalable to reduce power consumption, namely DCS. All our works are synthesized and simulated by the TSMC 65nm CMOS technology. It can perform high efficient computing power at FFTs/Energy.

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Chen YL, Hsu TY. Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches. In Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014. Institute of Electrical and Electronics Engineers Inc. 2015. p. 184-187. 7029577. (Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014). https://doi.org/10.1109/ISICIR.2014.7029577

Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches

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