Cost-effective multi-standard video transform core using time-sharing architecture

Yun Hua Tseng, Yuan Ho Chen, Chih Wen Lu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a cost-effective of two-dimensional (2-D) inverse discrete cosine transform (IDCT) that using time-sharing strategy scheme and hardware sharing architecture is proposed in multiple standards decoder of MPEG1/2/4, H264 and VC-1. The proposed design arranges different dimensional computations and calculates first-dimensional (1st-D) and second-dimensional (2nd-D) simultaneously in the 1-D IDCT transform to achieve high throughput rate and hardware utilization of 100%. Furthermore, the proposed one-dimensional (1-D) IDCT using distributed arithmetic (DA) algorithm to reduce hardware cost and is verified using TSMC 0.18 μm COMS process chip implementation. The measurement result shows that the inverse transform core has an operation frequency of 100MHz, and the maximum throughput rate is up to 400M-pels/s with 39K gate counts.

Original languageEnglish
Title of host publication2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509024391
DOIs
StatePublished - 12 Aug 2016
Event5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan
Duration: 4 May 20166 May 2016

Publication series

Name2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Conference

Conference5th International Symposium on Next-Generation Electronics, ISNE 2016
CountryTaiwan
CityHsinchu
Period4/05/166/05/16

Keywords

  • cost-efficitive
  • distributed arithmetic (DA)
  • multi-standard transform
  • time-sharing
  • Two-dimensional inverse discrete cosine transform (2D-IDCT)

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