We investigate the effects of oxidation and post-oxidation annealing temperatures on the breakdown of thin ( approximately equals 25nm ) SiO//2 dielectrics. We report a correlation between the amount of charge necessary for breakdown. Q//B//D, and the rate of positive charge trapping during high-field stressing. The correlation can be explained by a breakdown model which assumes that breakdown results from an enhancement of the electric field at the injecting interface due to the trapped positive charge. For annealing temperatures greater than approximately equals 900C the positive charge trapping rate increases markedly and as a result Q//B//D decreases significantly. This positive charge trapping in the gate insulator is the cause of the sensitivity of MOS devices to ionizing radiation, and has been attributed to viscous shear flow of the SiO//2. It was found that Q//B//D can be maximized by keeping the oxidation temperature below 1000C and that the optimum annealing temperature is approximately 900C.
|Number of pages||14|
|Journal||Proceedings - The Electrochemical Society|
|State||Published - 1 Dec 1986|