Cordic-based VLSI array for computing 2-D discrete Hartley transform

Jiun-In  Guo*, Chi Min Liu, Chein Wei Jen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

The inseparability of the 2-D DHT makes its VLSI design and hardware realization much more expensive. To conquer this problem, a new CORDIC-based 2-D DHT algorithm and the associated array design are presented in this paper. By exploiting the CORDIC property, the row/column decomposition can be successfully applied to reduce the computational complexity enormously without paying decomposition overhead. The presented array is featured with systolic computing style, the CORDIC structure of processing elements (PE's), low input/output (I/O) cost, and simple hardware.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherPubl by IEEE
Pages1571-1574
Number of pages4
ISBN (Print)0780312813
DOIs
StatePublished - 1 Jan 1993
EventProceedings of the 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA
Duration: 3 May 19936 May 1993

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

ConferenceProceedings of the 1993 IEEE International Symposium on Circuits and Systems
CityChicago, IL, USA
Period3/05/936/05/93

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