This work proposes a new CORDIC algorithm with merits of small number of rotation iterations, fast prediction of rotation sequence suited for parallel and pipelined operations, and fast simple variable scale factor decomposition and compensation. It has a close to the minimum number of 0.8 N iterations (including rotation and compensation) of the algorithm, but has the advantage of facilitating parallel and pipelined operations in realization over the latter algorithm.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 1998|
|Event||Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA|
Duration: 31 May 1998 → 3 Jun 1998