`Cool low power' 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology

R. V. Joshi*, Wei Hwang, S. C. Wilson, C. T. Chuang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations

Abstract

This paper describes power analysis at sub-zero temperatures for a high performance dynamic multiport register file (6 Read and 2 Write ports, 32 wordlines×64 bitlines) fabricated in 0.25 μm Silicon on Insulator (SOI) and bulk technologies. Based on the hardware it is shown that the performance of both register file and latch improves by 2-3.5% per 10 °C reduction in temperature. The standby power for SOI reduces by 1.5% to 3% per 10 °C temperature drop down to -30 °C. The SOI chip is shown to have more significant performance improvement at low temperatures compared to bulk chip due to the floating body effect which partially offsets the increase in the threshold voltages (Vt). The low temperature performance gain is attributed to reduction in capacitance (around 7-8%) and rest is due to dynamic threshold voltages. At -30 °C the register file is capable of functioning close to 1.02 GHz for read and write operations in a single cycle.

Original languageEnglish
Pages (from-to)203-206
Number of pages4
JournalProceedings of the International Symposium on Low Power Electronics and Design
DOIs
StatePublished - 3 Dec 2000
EventProceedings of the 2000 Symposium on Low Power Electronics and Design ISLPED'00 - Portacino Coast, Italy
Duration: 26 Jul 200027 Jul 2000

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