CONTROLLED-AVALANCHE SUPERLATTICE TRANSISTOR.

Albert Chin*, Pallab Bhattacharya

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

An n-p-n bipolar avalanche transistor is proposed. Controlled avalanche and large current output are achieved by incorporating in the collector junction a few periods of a symmetric or asymmetric multi-quantum-well in which electrons predominantly multiply. The theory of operation, materials growth by molecular beam epitaxy, and impact ionization data on the quantum-well and device performance are described. Optical gains as high as 140 are measured in these transistors.

Original languageEnglish
Pages255-264
Number of pages10
StatePublished - 1 Dec 1987

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