Configuration free SoC interconnect BIST methodology

Chau-Chin Su*, Wenliang Tseng

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

16 Scopus citations

Abstract

3-state drivers are modified to exhibit wired-logic properties in test mode, it does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously.

Original languageEnglish
Pages (from-to)1033-1038
Number of pages6
JournalIEEE International Test Conference (TC)
DOIs
StatePublished - 1 Dec 2001
EventInternational Test Conference 2001 Proceedings - Baltimore, MD, United States
Duration: 30 Oct 20011 Nov 2001

Keywords

  • Built-in self test
  • Design for testability
  • Interconnect testing
  • System-on-chip

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