Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip design

H. P. Wen*, C. Y. Lin, Y. L. Lin

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

4 Scopus citations

Abstract

We propose an Internet-based concurrent-simulation scheme to ease IP evaluation process between IP vendors and users. Complex system-on-a-chip design requires more and more IP modules from 3rd party vendors. What can be disclosed by the vendor without impairing its trade secrete and what needs to be examined by the user to gain satisfactory level of confidence are contradictory of each other. Via PLI interface functions and Internet protocol, our proposed software enables HDL simulators (Verilog) residing in both the vendor and user's sites to concurrently simulate the IP and SOC together. Only stimulus and response defined in the IP's I/O are exchanged between the sites. Therefore, the vendor need not to create a functional model (or encrypted code) for the IP while the user is assured what he/she simulates is what he will purchase. Beside simulation speed degradation due to communication overhead, the SOC design/debug process is exactly same as if the IP is in the user's hand. Our contribution will help all IP providers expose their IPs to all potential users without human intervention and IP right infringement concern.

Original languageEnglish
Pages (from-to)233-238
Number of pages6
JournalProceedings of the International Symposium on System Synthesis
DOIs
StatePublished - 1 Jan 2001
Event14th International Symposium on System Synthesis (ISSS'01) - Montreal, Que., Canada
Duration: 30 Sep 20013 Oct 2001

Keywords

  • Concurrent Simulation
  • Intellectual Property (IP)
  • IP Evaluation
  • System-on-a-Chip

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