Concurrent design analysis of high-linearity SP10T switch with 8.5 kV ESD protection

X. Shawn Wang, Xin Wang, Fei Lu, Chen Zhang, Zongyu Dong, Li Wang, Rui Ma, Zitao Shi, Albert Wang, Mau-Chung Chang, Dawn Wang, Alvin Joseph, C. Patrick Yue

Research output: Contribution to journalArticle

39 Scopus citations

Abstract

This paper discusses concurrent design and analysis of the first 8.5 kV electrostatic discharge (ESD) protected single-pole ten-throw (SP10T) transmit/receive (T/R) switch for quad-band (0.85/0.9/1.8/1.9 GHz) GSM and multiple-band WCDMA smartphones. Implemented in a 0.18 μm SOI CMOS, this SP10T employs a series-shunt topology for the time-division duplex (TDD) transmitting (Tx) and receiving (Rx), and frequency-division duplex (FDD) transmitting/receiving (TRx) branches to handle the high GSM transmitter power. The measured P-0.1 dB, insertion loss and Tx-Rx isolation in the lower/upper bands are 36.4/34.2 dBm, 0.48/0.81 dB and 43/40 dB, respectively, comparable to commercial products with no/little ESD protection in high-cost SOS and GaAs technologies. Feed-forward capacitor (FFC) and AC-floating bias techniques are used to further improve the linearity. An ESD-switch co-design technique is developed that enables simultaneous whole-chip design optimization for both ESD protection and SP10T circuits.

Original languageEnglish
Article number6850080
Pages (from-to)1927-1941
Number of pages15
JournalIEEE Journal of Solid-State Circuits
Volume49
Issue number9
DOIs
StatePublished - 1 Jan 2014

Keywords

  • CMOS
  • co-design
  • concurrent design
  • ESD
  • linearity
  • RF
  • SOI
  • SP10T
  • SPMT
  • switch

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