Comprehensive analysis of UTB GeOI logic circuits and 6T SRAM cells considering variability and temperature sensitivity

Vita Pi Ho Hu*, Ming Long Fan, Pin Su, Ching Te Chuang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A comprehensive comparative analysis of leakage-delay, stability and variability of GeOI logic circuits and 6T SRAM cells with respect to the SOI counterparts is presented. The UTB GeOI circuits show better power-performance than the bulk Ge-channel circuits, and preserve the leakage reduction property of stacking devices, while the band-to-band tunneling leakage of bulk Ge-channel devices cannot be reduced by stacking transistors. At Vdd = 1V and 400K, the delays of inverter, dynamic gates, latch and multiplexer for GeOI circuits are smaller than the SOI counterparts. For equal Ion design, the GeOI SRAM cells exhibit better μRSNM/σ RSNM and smaller cell leakage variation at both Vdd = 1V and 0.5V.

Original languageEnglish
Title of host publication2011 International Electron Devices Meeting, IEDM 2011
DOIs
StatePublished - 1 Dec 2011
Event2011 IEEE International Electron Devices Meeting, IEDM 2011 - Washington, DC, United States
Duration: 5 Dec 20117 Dec 2011

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2011 IEEE International Electron Devices Meeting, IEDM 2011
CountryUnited States
CityWashington, DC
Period5/12/117/12/11

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