Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations

Ming-Dou Ker*, Sheng Fu Hsu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

43 Scopus citations

Abstract

To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a current-limiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-μm CMOS technology.

Original languageEnglish
Article number1717497
Pages (from-to)461-472
Number of pages12
JournalIEEE Transactions on Device and Materials Reliability
Volume6
Issue number3
DOIs
StatePublished - 1 Sep 2006

Keywords

  • Holding voltage
  • Latch-up
  • Silicon-controlled rectifier (SCR)
  • System-level electrostatic discharge (ESD) test
  • Transient-induced latch-up (TLU)

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