Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier

Kuo Chiang Chang; Ching Hao Lin; Chih-Wei Liu

doi:10.1109/VLSI-DAT.2014.6834886

Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier

Kuo Chiang Chang, Ching Hao Lin, Chih-Wei Liu

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents an energy-efficient FIR filter architecture which applies CSD multiplication to satisfy the design considerations of power consumption, flexibility and area cost. The proposed architecture reduces number of partial product rows and shift range of each coefficient multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients. To mitigate this problem, this paper also presents a coefficient pre-processing flow to transform the original coefficients into applicable ones at design time to meet the restriction of the proposed multiplier. The simulation result reveals this technique can be applied for the computation of 97-tap filter. The design reduces up to 21.5% energy consumption per sample when compared with conventional Booth multiplier.

Original language	English
Title of host publication	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Publisher	IEEE Computer Society
ISBN (Print)	9781479927760
DOIs	https://doi.org/10.1109/VLSI-DAT.2014.6834886
State	Published - 1 Jan 2014
Event	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan Duration: 28 Apr 2014 → 30 Apr 2014

Publication series

Name	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Conference

Conference	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Country	Taiwan
City	Hsinchu
Period	28/04/14 → 30/04/14

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This output contributes to the following Sustainable Development Goal(s)

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Chang, K. C., Lin, C. H., & Liu, C-W. (2014). Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 [6834886] (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-DAT.2014.6834886

Chang, Kuo Chiang ; Lin, Ching Hao ; Liu, Chih-Wei. / Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

@inproceedings{69e7adaacd6d43c7aeaf7c7354532458,

title = "Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier",

abstract = "This paper presents an energy-efficient FIR filter architecture which applies CSD multiplication to satisfy the design considerations of power consumption, flexibility and area cost. The proposed architecture reduces number of partial product rows and shift range of each coefficient multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients. To mitigate this problem, this paper also presents a coefficient pre-processing flow to transform the original coefficients into applicable ones at design time to meet the restriction of the proposed multiplier. The simulation result reveals this technique can be applied for the computation of 97-tap filter. The design reduces up to 21.5% energy consumption per sample when compared with conventional Booth multiplier.",

author = "Chang, {Kuo Chiang} and Lin, {Ching Hao} and Chih-Wei Liu",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/VLSI-DAT.2014.6834886",

language = "English",

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series = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

publisher = "IEEE Computer Society",

booktitle = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

address = "United States",

note = "null ; Conference date: 28-04-2014 Through 30-04-2014",

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Chang, KC, Lin, CH & Liu, C-W 2014, Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. in Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014., 6834886, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, IEEE Computer Society, 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, Hsinchu, Taiwan, 28/04/14. https://doi.org/10.1109/VLSI-DAT.2014.6834886

Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. / Chang, Kuo Chiang; Lin, Ching Hao; Liu, Chih-Wei.

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. 6834886 (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents an energy-efficient FIR filter architecture which applies CSD multiplication to satisfy the design considerations of power consumption, flexibility and area cost. The proposed architecture reduces number of partial product rows and shift range of each coefficient multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients. To mitigate this problem, this paper also presents a coefficient pre-processing flow to transform the original coefficients into applicable ones at design time to meet the restriction of the proposed multiplier. The simulation result reveals this technique can be applied for the computation of 97-tap filter. The design reduces up to 21.5% energy consumption per sample when compared with conventional Booth multiplier.

AB - This paper presents an energy-efficient FIR filter architecture which applies CSD multiplication to satisfy the design considerations of power consumption, flexibility and area cost. The proposed architecture reduces number of partial product rows and shift range of each coefficient multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients. To mitigate this problem, this paper also presents a coefficient pre-processing flow to transform the original coefficients into applicable ones at design time to meet the restriction of the proposed multiplier. The simulation result reveals this technique can be applied for the computation of 97-tap filter. The design reduces up to 21.5% energy consumption per sample when compared with conventional Booth multiplier.

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Chang KC, Lin CH, Liu C-W. Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society. 2014. 6834886. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). https://doi.org/10.1109/VLSI-DAT.2014.6834886

Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier

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