This paper presents an energy-efficient FIR filter architecture which applies CSD multiplication to satisfy the design considerations of power consumption, flexibility and area cost. The proposed architecture reduces number of partial product rows and shift range of each coefficient multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients. To mitigate this problem, this paper also presents a coefficient pre-processing flow to transform the original coefficients into applicable ones at design time to meet the restriction of the proposed multiplier. The simulation result reveals this technique can be applied for the computation of 97-tap filter. The design reduces up to 21.5% energy consumption per sample when compared with conventional Booth multiplier.