Complexity-effective implementation of programmable FIR filters using simplified canonic signed digit multiplier

Kuo Chiang Chang, Ching Hao Lin, Chih-Wei Liu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents an energy-efficient FIR filter architecture which applies CSD multiplication to satisfy the design considerations of power consumption, flexibility and area cost. The proposed architecture reduces number of partial product rows and shift range of each coefficient multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients. To mitigate this problem, this paper also presents a coefficient pre-processing flow to transform the original coefficients into applicable ones at design time to meet the restriction of the proposed multiplier. The simulation result reveals this technique can be applied for the computation of 97-tap filter. The design reduces up to 21.5% energy consumption per sample when compared with conventional Booth multiplier.

Original languageEnglish
Title of host publicationTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
PublisherIEEE Computer Society
ISBN (Print)9781479927760
DOIs
StatePublished - 1 Jan 2014
Event2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan
Duration: 28 Apr 201430 Apr 2014

Publication series

NameTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Conference

Conference2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
CountryTaiwan
CityHsinchu
Period28/04/1430/04/14

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