A new ESD protection circuit with complementary SCR structures and junction diodes is proposed. This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6-µm CMOS SRAM technology with LDD process. The proposed ESD protection circuit can be free of VDD-to-VSS latchup issue under 5-V VDD operation by means of base-emitter shorting method. To compensate the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform high ESD failure threshold in a small layout area, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications.