Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

Ming-Dou Ker*, Chung-Yu Wu, Hun Hsien Chang, Tao Cheng, Tain Shun Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

11 Scopus citations

Abstract

There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to Vss and Vdd power lines. The dc switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area.

Original languageEnglish
Article number5099908
Pages (from-to)833-836
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 1 Jan 1995
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: 30 Apr 19953 May 1995

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