Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

Ming-Dou Ker*, Chung-Yu Wu, Hun Hsien Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

45 Scopus citations

Abstract

There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines. The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid the unexpected ESD damages on internal circuits. Experimental results show that it can perform excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit. The device characteristics under high-temperature environment of up to 150°C is also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.

Original languageEnglish
Pages (from-to)588-598
Number of pages11
JournalIEEE Transactions on Electron Devices
Volume43
Issue number4
DOIs
StatePublished - 1 Apr 1996

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